usb device controller M66290AGP/fp mitsubishi 1 description the m66290a is a general purpose usb (universal serial bus) device controller compatible with the usb specification version 1.1 and corresponds to full speed transfer. built-in transceiver circuits meet all transfer type which is defined in usb. m66290a has fifo of 3k bytes for data transfer and can set 6 endpoints (maximum). each endpoint can be set programmable of its transfer condition, so can correspond to each device class transfer system of usb. features usb specification 1.1 compliant built-in usb transceiver circuit supports full speed (12 mbps) transmission supports all four usb transfer type : control transfer bulk transfer isochronous transfer interrupt transfer built-in fifo (3 kbytes) for endpoint up to 6 endpoint (ep0 to ep5) selectable outline M66290AGP:48p6q-a(lqfp) m66290afp:48p6x-a(tqfp) data transfer condition selectable for each endpoints (ep1 to ep5) data transfer type (bulk, isochronous and interrupt) transfer direction (in/out) buffer size of fifo (maximum 1024 bytes) double (toggle) buffer configuration continuous transfer mode (buffering up to 1 kbytex2) max packet size supports 4 input clock frequencies input clock : 6/12/24/48 mhz built-in pll which has an oscillation buffer and outputs at 48 mhz supports both 8-bit and 16-bit dma transfers 16-bit cpu bus interface 3.3v single power source built-in j tag application printer , scanner , dsc , dvc pc camera , multimedia speaker , terminal adapter etc. support all pc peripheral using full speed usb 37 38 39 40 41 42 43 44 45 46 47 48 23 22 21 20 19 18 17 16 15 14 13 m66290afp 24 xout v cc gnd xin a1 a2 a3 a4 a5 a6 d0 d1 oscillator output d12 d13 d14 d15 int rd wr rst cs dreq dack test2 test2 input interrupt dma request dma acknowledge c mitsubishi electric corporation ver.1.0 oct. 27, 2000 pin configuration (top view) address bus data bus write strobe read strobe chip select reset data bus oscillator input M66290AGP or
usb device controller M66290AGP/fp mitsubishi 2 xin cs rd wr int dreq 68 d+ d- gnd 2 15 36 clock control (oscillator/ pll ) serial interface engine device control unit a6 to 1 cpu register endpoint buffer (3kbyte fifo) usb peripheral circuit dack v cc 1 16 35 4 3 vbus 13 14 6 tron 5 xout 45 44 43 42 17 22 23 40 d15 to 0 68 47 48 46 41 7 rst test2 test1 8 9 10 11 12 trst tck tms tdi tdo to block descriptions the m66290a contains usb transceiver, oscillation circuit, pll, serial interface engine, endpoint buffer, device control unit, and cpu register. usb transceiver usb transceiver is consisted of differential driver and differential receiver. and is compatible with usb specification version 1.1 and corresponds to full speed transfer mode. serial interface engine (sie) sie handles protocol layer as follows. extract a usb 12mhz clock serial-parallel data conversion sync detection nrzi encode and decode bit stuffing and destuffing crc generator and checker device control unit (dcu) dcu controls the device state sequence, control transfer sequence, and so on. endpoint buffer this is a fifo buffer for transmit and receive between endpoints. except for ep0 for control transfer, five endpoints (ep1 to ep5) can be set. cpu register this is an interface block with cpu. oscillator/pll this block oscillates the internal operation clock source of 48mhz. external clock of 6/12/24/48mhz can be input. usb peripheral circuit detect the connection and the shutdown of usb by the vbus input. connect the vbus of usb bus to or the 5v power supply to vbus input. connect the tron output to d+ pull-up resistor of 1.5kohm. on/off of the pull-up resistor is controlled by the register. block diagram usb transceiver to
usb device controller M66290AGP/fp mitsubishi 3 oscillato r output oscillato r input - - 1 1 generate an internal clock. input or output of internal clock oscillator. when use as a crystal oscillator, connect a crystal between xin and xout. if an external clock is used, input it to xin, and xout must be opened. others output xout input xin 1 reset "l" level initializes the register or the counter of m66290a. input rst jtag interface 1 1 test2 input (built-in pull down resistor) input for the test. keep "l" level or open. test1 input (built-in pull down resistor) input for the test. keep "l" level or open. input test2 input test1 gnd cpu interface dma interface usb interface 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 ground power supply pin v cc output input test data output data output from jtag. if the jtag is not used, keep open. tdo test data input (built-in pull up resistor) data input to jtag. if jtag is not used, keep "h" level or open. tdi input test clock input (built-in pull down resistor) clock input to jtag. if jtag is not used, keep "l" level or open. tck tms input test mode input (built-in pull up resistor) mode set input to jtag. if jtag is not used, keep "h" level or open. test reset input (built-in pull up resistor) reset input of jtag. even if the jtag is not used, jtag circuit must be initialized. input "l" level to initialize like the rst input. input trst dma acknowledge fifo access by dma transfer is available in "l" level input dack tron output connect to the d+ pull-up resistor of 1.5kohm. on/off control of the pull-up resistor is available. vbus input (built-in pull down resistor) connect to the vbus of usb bus or to the 5v power supply. connection or shutdown of the vbus can be detected. output input tron vbus usb data(-) d- of usb. connect the external resistor serially. input/ output d- input/ output usb data(+) d+ of usb. connect the external resistor serially. d+ dreq output dma request dma transfer request to endpoint fifo int output interrupt "l" level requests interrupt to system input rd read strobe register data can be read when "l" level wr input 1 write strobe input data is written into the register by the positive edge 1 chip select "l" level enables to communicate with m66290a input cs address bus address bus to access the register from the system input a6 to a1 data bus data bus to access the register from the system input/ output d15 to d0 6 16 item pin name input/ function number of pin descriptions
usb device controller M66290AGP/fp mitsubishi 4 usb data transfer descriptions m66290a is a usb device controller correspond to all the four types of transfer (control, bulk, isochronous, and interrupt transfer), which is compatible to usb specification 1.1. m66290a acts usb functions as below automatically. (1) bit stuffing/destuffing (2) crc generate/check (3) nrzi encode/decode (4) packet handling (5) usb address check (6) bus error handling therefore, when cpu transact the operations as follows, usb transfer is realized. (1) response to the control transfer request (2) permission of store and transmission of the transmit data into the endpoint buffer. (or read of the received data from the endpoint buffer) (3) stall handling (4) suspend/resume handling below are the descriptions about the data transfer. data receive in data receive, there are differences of its function between setup transaction and out transaction. in setup transaction, w hen received device request from host, 8byte request is always stored into four resistors. when request data is received correctly,sends back ack packet to host and at the same time, occurs interrupt to cpu and urge cpu to read request. in out transaction, after m66290a received out token packet, host transmits data packet. if packet of maximum packet size or short packet is stored into the endpoint fifo of m66290a, and moreover, error is not occurred in that transfer, m66290a transmits ack packet to host and informs cpu that the data was received by occurring buffer ready interrupt. if usb protocol error is occurred in the host data which received via usb bus, or if the endpoint fifo is full, m66290a does not transmit ack packet to host. host knows that the error occurred because the ack packet does not come, and take a step such as data resend. data transmit when the data of endpoint fifo, which corresponds to transmit request by in token packet, is ready, m66290a transmit the corresponded data packet to usb bus. if the ack packet come from the host for the transmitted data packet, a transaction completed and the endpoint fifo becomes empty and urge cpu to write the next transmit data by buffer ready interrupt. if the transmit data, which correspond to transmit request by in token packet, is not exist in the endpoint fifo, m66290a transmit nak packet to host when received in token packet from host and occurs interrupt and request cpu to write transmit data. when m66290a received in token packet again from host, m66290a transmits the data which is written. if error is not occurred in that transfer, host transmit ack packet and if m66290a received it normally, a transaction completed. if usb protocol error is occurred in the data which is transmitted via usb bus, host does not transmit ack packet, so m66290a watch and wait until receive in token packet, with keeping the data to be transmitted.
usb device controller M66290AGP/fp mitsubishi 5 - 0000h 0000h r/w - 0000h 0000h r/w - - - - - - - - - - - - - - 0000h 0000h r/w interrupt status register2 1ch - 0000h 0000h r/w interrupt enable register2 14h - 0000h 0000h - 0000h 0000h - 0000h 0000h note 2 0000h 0000h - 0000h 0000h - - 0000h - - 0000h - - 0000h - - 0000h - 0000h - 0008h - 0000h - 0000h - 0800h - xxxx - 0000h - 0000h - 0800h - xxxx - 0000h - 0800h - xxxx - - 0000h - - 0040h - - 0000h - - 0040h - - 0000h - - 0040h - - 0000h - - 0040h - - 0000h 0000h address name r/w 0000h - - - usb 0000h 0000h 0000h - s/w 0000h 0000h 0000h h/w r/w r/w r/w (note 2) r/w r/w r/w r/w r r r r r r/w (note 2) r/w r/w r/w (note 2) r r/w r/w r/w r/w r/w (note 2) r/w r/w r/w (note 2) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ep5 configuration register0 ep4 configuration register1 ep4 configuration register0 ep3 configuration register1 ep3 configuration register0 ep2 configuration register1 ep2 configuration register0 ep1 configuration register1 ep1 configuration register0 reserved dma_fifo data register dma_fifo control register dma_fifo selection register reserved cpu_fifo data register cpu_fifo control register cpu_fifo selection register reserved ep0 continuous transmit data length ep0_fifo data register ep0_fifo control register ep0_fifo selection register reserved auto-response control register ep0 packet size register control transfer control register length register index register value register request register interrupt status register3 interrupt status register1 interrupt status register0 interrupt enable register3 interrupt enable register1 interrupt enable register0 reserved isochronousstatus register usb_address register reserved sequence bit clear register remote wake-up register usb operation enable register 4eh to 5eh 70h 6eh 6ch 6ah 68h 66h 64h 62h 60h 4ch 4ah 48h 46h 44h 42h 40h 38h to 3eh 36h 34h 32h 30h 2eh 2ch 2ah 28h 26h 24h 22h 20h 1eh 1ah 18h 16h 12h 10h 0ch to 0eh 0ah 08h 06h 04h 02h 00h control register table n ote 1 : detail description is mentioned later. note 2 : some are read only. shows the reset status by receiving usb reset. " - " shows that the previous status is kept. write into reserved address is inhibited. below is the table of registers of m66290a. bit width of all register is 16bits. in reset item, "h/w" shows the reset status by external rst input, "s/w" shows reset status by usbe register, and "usb"
usb device controller M66290AGP/fp mitsubishi 6 functional and register descriptions we explain about function and register constitution of m66290a dividing into four items as follows. (1) system control (2) interrupts (3) control transfer/enumeration (4) endpoints and fifo control (1) system control clock clock of 48mhz is needed for internal operations of m66290a. built in pll enables to input external clock of 6/12/ 24/48mhz. selection of it is realized by the xtal of "usb operation enable register". when use external clock of 48mhz, pll is not needed, so set to pll operation disable. built in oscillation circuit enables to supply clock by self oscillation. reset s/w reset by the register set (usbe), different from the hardware reset, keeps the value of register of usb operation enable register, fifo relational register, control transfer relational register,endpoint setting register, and so on. and i n usb reset (when more than 2.5us of se0 state is continued on d+, d- terminal), the value of register is kept except for "interrupt status register 0" and "usb_address register" as to d etails of reset state, see each item of register. d+ pull-up resistor control function to set the register, external tron output is controlled and can control the on/off of pull-up resistor (1.5kohm) on usb d+ line. and when use this function, device state shifts to address state after outputs remote wakeup signal, so it is needed to set up again the device state to configured state. change of set up of device state can be done in s/w control mode. remote wakeup signal is a signal to set usb bus to idle state after output k-state of 10ms length. if this remote wakeup function is set up immediately after detected suspend, usb bus idle state is kept for 2ms and then shifts to k state output. (because usb bus idle state must be kept for 5ms minimum until transmit of remote wakeup signal, on the other hand after detect suspend, usb idle state is continued for 3ms) sequence toggle bit clear function in each endpoint of ep0 to ep5, data pid can be reset independently and also can appoint pid of data0. by this function, management of sequence toggle bit in transfer after reset pid, is done by h/w automatically. error information in isochronous transfer in isochronous transfer there is not retry function of transmit/receive, because the handshake from receiver to transmitter is not returned not to disturb the time equivalent data transfer. m66290a has enough information function which enables firmware to manage incorrect transfer in case of transfer error occurred in isochronous transfer. information which m66290a can inform is, over run error, under run error, received data error (crc error, bit stuffing error), and frame number. software control mode in software control mode, it is available to set up (write) from cpu as follows, usb_address register (usb_addr), device state register (dvsq), control transfer stage register (ctsq). normally, use this mode with off. to set the "usb operation enable register", it can be set the device to standby state. oscillation is halted (clock input halted) by xcke, pll operation is halted by pllc, and clock supply to usb block is halted by scke. to prevent unstable behavior by unstable clock, clock supply to usb block must be obeyed the process, that is, enables clock input by xcke, wait until oscillation stabilized, start pll by pllc, wait until oscillation stabilized (less than 1ms), and start clock supply to usb block by scke. remote wakeup function when device is in suspended state, outputs remote wakeup signal and can cancel suspended state to receive resume from usb. remote wakeup function is only effective in suspended state in which device state shifts from configured state, so don't use to other device state. xin xout m66290a rf rd c1 c2 xin xout m66290a clock input open (1) in case of crystal oscillation (2) in case of external clock input figure 1. xin and xout connections xtal place the parts as near the terminal as possible
usb device controller M66290AGP/fp mitsubishi 7 - - 0 w/r 0 : normal operation 1 : software control mode operation software control mode sctr 1 write/read "0" - - 0 w/r - - 00 w/r - - 0 w/r - - 0 w/r - - 00 w/r - - 0 w/r reserved 0 7 to 2 9, 8 10 11 13, 12 14 usbe 0 : usb module disable (s/w reset) 1 : usb module enable usb module enable x0 : tron port ="hi-z" 01 : tron port ="l" 11 : tron port ="h" this fields selects tron output state, and it is effective when external vbus input is "h" level (5v). if external vbus input is "l", these bits can be set but tron output does not operate. tr_on output control tr_on [1:0] 0 : usb transceiver disable 1 : usb transceiver enable in suspend state, resume signal can be received even if usb transceiver disabled. usb transceiver power control usbpc 0 : internal clock (sck) disable 1 : internal clock (sck) enable internal clock enable scke crystal select xtal[1:0] 00 : 1/1 division ( external 48mhz input) 10 : 1/2 division (external 24mhz input ) 01 : 1/4 division ( external 12mhz input ) 11 : 1/8 division ( external 6mhz input ) 0 : pll disable 1 : pll enable when use external clock of 48mhz, set to pll disable. pll control pllc - - 0 w/r 0 : oscillator disable (clock input disable) 1 : oscillator enable (clock input enable) xcke 15 oscillator enable bit bit name name function w/r usb s/w h/w reset sctr tr_on[1:0] xtal[1:0] usbpc scke pllc xcke usbe d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 name - 0 0 w/r write/read "0" when cpu write "1" to wkup for remote wake-up, m66290a outputs k-state for 10ms, and return to bus idle-state. (remote wake-up signal) this bit returns to "0" automatically after suspend is canceled. if "1" is written into this bit after detected suspend, bus idle state is kept for 2ms and after then shifts to k state output. reserved 0 remote wake-up wkup 15 to 1 bit bit name function w/r usb s/w h/w reset wkup d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 ( 1-2 ) remote wake-up register (address : 02h) (1-1) usb operation enable register (address : 00h)
usb device controller M66290AGP/fp mitsubishi 8 bit name - 00h 00h w/r write/read "0" sqclr [5:0] when write "1" into the bit which is correspond to the number of endpoint, sequence toggle bit of that endpoint is cleared and appoint the data0 by the data pid of next transmission. write "1" into the bit after set the response pid of the endpoint, which clears sequence toggle bit, to nak("00") . transfers after the transfer appointed, sequence toggle bit is controlled by h/w. in usb reset, sequence toggle bit of each endpoint is not cleared. if "0" is written into this bit, flag is not changed. read data of this bit is always "0". reserved 5 to 0 sequence toggle bit clear 15 to 6 bit name function w/r usb s/w h/w reset sqclr[5:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 (1-3) sequence bit clear register (address : 04h) write/read "0" bit usb address which is assigned by host is stored. after stored the address, transaction is done only to the token packet which is transmitted to this address. (if s/w control mode is set, write operation is available) 00h 00h 00h r usb_ addr [6:0] reserved 6 to 0 usb_address register 15 to 7 bit name name function w/r usb s/w h/w reset usb_addr[6:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 (1-4)usb address register (address : 08h)
usb device controller M66290AGP/fp mitsubishi 9 reset function name bit - 0 0 w/r select the renewal timing of the flame number to be stored to frnm[10:0]. 0 : renew the flame number when sof is received . 1 : in isochronous transfer, renew the flame number at the timing of the end of transaction. frame number mode fmod 11 - 000h 000h r - 0 0 w/r write/read "0" stores the flame number. the timing to renew the stored flame number is selectable by set fmod. frame number 10 to 0 13 to 12 14 frnm [10:0] reserved in isochronous transfers(out), if the received data has crc or bit stuffing error, this flag is set at the timing of the end of transaction. when a state above is occurred, endpoint buffer notready interrupt is occurred. when "0" is written, status flag is cleared. when "1" is written, flag is not changed. receive data error crce - 0 0 w/r in iso chronous transfers (out/in), when over-run or under-run is occurred to the endpoint buffer, this flag is set at the timing of the receive end of the out/in token packet. over run is occurred when delayed to read the received data from the endpoint buffer, and means that could not received. over run is occurred when the direction of transmission is out. also the received data has crc or bit stuffing error, this flag is set. under run is occurred when delayed to write the transmit data into the endpoint buffer, and means that could not transmitted. under-run is occurred when the direction of transmission is in. when a state above is occurred, endpoint buffer notready interrupt is occurred. when "0" is written, status flag is cleared. when "1" is written, flag is not changed. ovrn 15 over run error bit name w/r usb s/w h/w fmod crce ovrn frnm[10:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 ( 1-5 ) isochronous status register ( address : 0ah )
usb device controller M66290AGP/fp mitsubishi 10 (2) interrupts there are eight factors of interrupt to cpu. when interrupt occurred, the factor can be known to refer to "interrupt status register 0" and "interrupt status register 1". these interrupts can be set of its enable/disable independently to set "interrupt enable register 0" and "interrupt enable register 1". if disable is set, interrupt is not occurred but interrupt status flag is set. each factor of interrupt is shown in the table below, and also describes below the interrupt conditions and how to deal with the interrupt. vbus vbus interrupt (connec/shut-down detect) status bit name change of the vbus input (both "l" to "h" and "h" to "l") vbus resm resume detect interrupt abstract of interrupt factor resume signal received in suspended sofr sof detect interrupt received sof dvst device state transition interrupt shift of device state dvsq[2:0] ctrt control transfer stage transition interrupt stage shift of control transfer ctsq[2:0] bemp endpoint buffer empty/size-over interrupt in each endpoint, when data transmit of all buffer is ended and buffer is empty, or in out transfer, received packet which exceeds max packet size. epb_emp_ovr[5:0] intn endpoint buffer not ready interrupt when buffer is in not ready state (sie cannot read and write) to in/out token of each endpoint. epb_nrdy[5:0] intr endpoint buffer ready interrupt when buffer of each endpoint became ready (read enable/write enable) epb_rdy[5:0] relational status bit vbus (connect/shut down) interrupt (vbus) interrupt occurs when vbus input state is changed (both "l" to "h" and "h" to "l"). to know vbus input state, confirm the vbus bit of interrupt status register 0. confirmation of vbus bit must be done after enabled internal clock operation. this interrupt can be occurred even if the internal clock(sck) is halted. to clear the status flag, enables the internal clock(sck) in operation and then write "0". if the internal clock(sck) is halted, status flag can not be cleared. this interrupt is useful to detect connect/shut-down of usb for prepareration/close of usb transfers. summary of interrupts resume detect interrupt (resm) if device state is in suspended state and resume interrupt enable flag is set, interrupt occurs when usb bus state is changed ("j" to "k" or "se0"). this interrupt can be occurred even if the internal clock(sck) is halted. to clear the status flag, set the internal clock(sck) in operation and then write "0". if the internal clock(sck) is halted, status flag can not be cleared. sof detect interrupt (sofr) interrupt occurs when detect sof. device state transition interrupt (dvst) m66290a manages the device state by h/w. it manages powered, default, address, configured, and suspended state. device state can be known to refer to "interrupt status register 0". as to device state shift, see the item of "device state shift" in "(3) control transfer/emulation" in the latter part. device state transition interrupt occurs when device state shifted. the number of factors is four, that is, usb bus reset detect, suspend detect, execution of "set address", and execution of "set configuration". usb reset is detected when se0 state over 2.5us is continued on d+, d- terminal. suspend is detected when idle state over 3ms is continued on d+, d- terminal.
usb device controller M66290AGP/fp mitsubishi 11 each of "set address" and "set configuration" execution detects the device state shift by analyzing the device request in control transfer. each of these four factors can be set of its interrupt to enable or disable by setting the corresponded bit of interrupt enable register 0. for example by using this interrupt, when usb bus reset is detected, a step to usb bus is available and when suspend is detected, a step to shift device to low power consumption. control transfer stage transition interrupt (ctrt) m66290a manages the sequence of control transfer by h/w. each stage of control transfer, such as setup stage, data stage, and status stage can be known to refer to the "interrupt status register 0". control transfer stage transition interrupt is occurred when the control transfer stage is shifted. there are five factors, that is, setup stage end, control write transfer stage shift, control read transfer stage shift, control transfer end, and control transfer sequence error. except for setup stage, each of these four factors can be set of its interrupt to enable or disable by setting the corresponded bit of interrupt enable register 0. as to control transfer sequence error which can be recognized by h/w, refer to "control transfer stage shift" in the item of "(3) control transfer/enumeration" in the latter part. endpoint buffer empty/size-over interrupt (bemp) interrupt factor is different by transfer direction of endpoint. 1. in case of transfer direction is in in each endpoint, interrupt occurs when transmission ended of all data which is stored in the buffer. by this interrupt, when endpoint is set to double buffer, end of data transmission of all data of the buffer can be known. and also can know the end of data transmission of control read transfer in endpoint 0 (ep0). 2. in case of transfer direction is out in each endpoint, interrupt occurs in data packet receive when received packet which exceeds the maximum packet size. by refer to epb_emp_ovr[5:0] of interrupt status register, it can be known which endpoint occurred the interrupt. endpoint buffer not ready interrupt (intn) when the buffer is in not ready state to in/out token of each endpoint, interrupt occurs at the timing of token packet receive end. by refer to epb_nrdy[5:0] of interrupt status register 1, it can be known which endpoint occurred the interrupt. if endpoint is set to isochronous transfer, when over-run/ under-run error is occurred, interrupt occurs at the timing of token packet receive end. and if it is set to isochronous (out), if received data has error such as crc error, interrupt occurs at the timing of transaction end. the variety of error in isochronous transfer is known to refer "isochronous status register". endpoint buffer ready interrupt (intr) interrupt occurs when the buffer of each endpoint became ready (read/write is available). it can be known which endpoint occurred the interrupt to refer epb_rdy[5:0] of interrupt status register 1. according to the endpoint and its access mode, the factor of interrupt is different as follows. 1. in case of ep0 interrupt occurs when receive (out) buffer of endpoint 0 became ready. if it is set to control write continuous receive mode, when continuous receive of 255 bytes ended or when received short packet, interrupt occurs. interrupt is not occurred even if the transmit buffer became ready. 2. in case of ep1 to ep5, when cpu access interrupt occurs when the buffer of each endpoint became ready. 3. in case of ep1 to ep5, when dma access if the transfer direction is set to out, interrupt occurs when received short data packet and then ended dma transfer. interrupt is not occurred if the transfer direction is set to in.
usb device controller M66290AGP/fp mitsubishi 12 figure 2. shows the examples of interrupt output timing (1) endpoint buffer ready interrupt (ex.out transaction) usb pid sync addr endp crc eop sync pid data crc eop sync pid eop out token packet data packet hand shake packet (ack) int output buffer becomes ready (read enable) and interrupt occurs (2) endpoint buffer not ready interrupt (ex.out transaction) usb pid sync addr endp crc eop sync pid data crc eop sync pid eop out token packet data packet hand shake packet (nak) int output buffer is in not ready (receive disable) and interrupt occurs (3) endpoint buffer not ready interrupt (ex.in transaction) usb pid sync addr endp crc eop sync pid eop in token packet hand shake packet (nak) int output buffer is in not ready (transmit disable) and interrupt occurs figure 2. examples of interrupt output timing
usb device controller M66290AGP/fp mitsubishi 13 endpoint5-0 buffer ready interrupt enable reset name bit name bit if this bit is "1", then the ctrt flag is set when shifted to status stage in control write transfer. - 0 0 w/r control write transfer status stage wdst endpoint5-0 buffer empty/size error interrupt enable - 0 0 w/r 0 : disable 1 : enable - 0 0 w/r - 0 0 w/r - 0 0 w/r - 0 0 w/r - 0 0 w/r - 0 0 w/r - 0 0 w/r - 0 0 w/r - 0 0 w/r - 0 0 w/r - 0 0 w/r - 0 0 w/r - 0 0 w/r control transfer sequence error if this bit is "1", then the ctrt flag is set when control transfer completed (when the status stage completed normally). control transfer complete 0 : disable 1 : enable if this bit is "1", then the ctrt flag is set when shifted to status stage in control read transfer. control read transfer status stage if this bit is "1", then the dvst flag is set when detected suspend. suspend detect if this bit is "1", then the dvst flag is set after executed setconfigration. set configration execute if this bit is "1", then the dvst flag is set after executed setaddress. set address execute if this bit is "1", then the dvst flag is set when detected usb reset. usb reset detect 0 : disable 1 : enable endpoint5-0 buffer not ready interrupt enable 0 : disable 1 : enable 1 2 3 4 5 6 7 8 cmpl rdst susp scfg sadr urst intre intne 0 9 10 11 12 13 14 serr if this bit is "1" then the ctrt flag is set when error occurred in the sequence of control transfer. bempe 0 : disable 1 : enable control transfer interrupt enable ctre 0 : disable 1 : enable device state interrupt enable dvse sof interrupt enable sofe 0 : disable 1 : enable resume interrupt enable rsme - 0 0 w/r 0 : disable 1 : enable vbse 15 vbus interrupt enable function w/r usb s/w h/w wdst bempe rdst intne ctre serr cmpl susp scfg sadr urst intre dvse sofe rsme vbse d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 ( 2-1 ) interrupt enable register 0 (address : 10h )
usb device controller M66290AGP/fp mitsubishi 14 ( 2-2 ) interrupt enable register 1( address : 12h ) - 00h 00h w/r write/read "0" endpoint5-0 buffer empty/size error interrupt enable 0 : disable 1 : enable the number of endpoint is correspond to each bit one by one. 5 to 0 epb_ empe [5:0] reserved 15 to 6 bit bit name name function w/r usb s/w h/w reset (2-4 ) interrupt enable register 3 ( address : 16h ) epb_empe[5:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 endpoint5-0 buffer not ready interrupt enable epb_nre [5:0] - 00h 00h w/r write/read "0" 0 : disable 1 : enable the number of endpoint is correspond to each bit one by one. 5 to 0 reserved 15 to 6 bit bit name name function w/r usb s/w h/w reset (2-3 ) interrupt enable register 2 ( address : 14h ) epb_nre[5:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 endpoint5-0 buffer ready interrupt enable epb_re [5:0] - 00h 00h w/r write/read "0" 0 : disable 1 : enable the number of endpoint is correspond to each bit one by one. 5 to 0 reserved 15 to 6 bit bit name name function w/r usb s/w h/w reset epb_re[5:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14
usb device controller M66290AGP/fp mitsubishi 15 reset function name bit the factor is different by the direction of the transfer of each endpoint. in each endpoint, this bit changes to "1" when the transmission of all stored data is completed (direction:in) and when received the packet which is exceeded to maximum packet size (direction:out). the endpoint which occurs the interrupt can be checked to see the epb_emp_ovr[5:0]. this flag is cleared to clear the status flag of epb_emp_ovr[5:0]. - 0 0 r - 0 0 w/r 1 0 0 w/r - 0 0 w/r - 0 0 w/r endpoint5-0 buffer empty/size error interrupt bemp 10 this bit changes to "1" when the stage of control transfer is shifted. there are five factors, that is, setup stage end, control write transfer status stage shift, control read transfer status stage shift, control transfer end, and control transfer sequence error. four factors, except for setup stage end, can be masked by the corresponded bit of the "interrupt enable register0". if "0" is written, status flag is cleared. if "1" is written, flag is not changed. control transfer stage transition interrupt this bit changes to "1" when device state shifted. there are four factors, that is, usb reset detect, suspend detect, "set address" execution, and "set configuration" execution. these four factors can be masked by the corresponded bit of "interrupt enable register0" . if "0" is written, status flag is cleared. if "1" is written, flag is not changed. device state transition interrupt this bit changes to "1" when detected sof. if "0" is written, status flag is cleared. if "1" is written, flag is not changed. sof detect interrupt this bit changes to "1" when usb bus state changed("j" to "k" or "se0") under the condition that resume interrupt enable flag is set. this bit is set even if the internal clock (sck) is in halt state. if "0" is written after enabled internal clock as operation, status flag is cleared. but if internal clock is in halt state, flag is not cleared. if "1" is written, flag is not changed. resume detect interrupt this bit changes to "1" when vbus input changed both "0" to "1" and "1" to "0". as to the vbus input state, confirm to see the bit of vbus input port. this bit is set even if the internal clock (sck) is in halt state. if "0" is written after enabled internal clock as operation, status flag is cleared. but if internal clock is in halt state, flag is not cleared. if "1" is written, flag is not changed. vbus interrupt sofr 11 12 13 14 ctrt dvst resm - 0 0 w/r vbus 15 bit name w/r usb s/w h/w bemp intn valid dvsq[2:0] ctsq[2:0] ctrt vbus intr dvst sofr resm vbus d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 (2-5) interrupt status register 0 ( address : 18h)
usb device controller M66290AGP/fp mitsubishi 16 bit bit name name function reset - 0 0 r this bit changes to "1" at the timing of token packet receive end when buffer respond nak, of its not ready state, to in/out token of each endpoint. the endpoint which occurred the interrupt is checked to see epb_nrdy[5:0]. this flag is cleared to clear the status flag of epb_nrdy[5:0]. endpoint5-0 buffer not ready interrupt enable intn 9 - 0 0 r this bit changes to "1" when the buffer of each endpoint became ready (read/write enable). the endpoint which occurred the interrupt is checked to see epb_rdy[5:0]. this flag is cleared to clear the status flag of epb_rdy[5:0]. endpoint5-0 buffer ready interrupt enable intr 8 r w/r r - 0 0 - 000 000 001 000 000 ext. ext. ext. r 000: powered state 001: default state 010: address state 011: configured state 1xx: suspended state device state can be known. as to the device state shift, refer to fig.5 in the later part. when detect usb reset, this becomes 001: default state automatically. when detect suspend, this becomes 1xx: suspended state automatically. whatever the automatic response mode is, this becomes 010: address state after executed set_address request, and becomes 011: configured state after executed set_configuration request. (write operation is available when s/w control mode is set) device state this bit changes to "1" when received setup packet. this flag does not the factor of interrupt. when "0" is written, status flag is cleared . when "1" is written, flag is not changed . setup packet detect 000 : idle or setup stage 001 : control read transfer data stage 010 : control read transfer status stage 011 : control write transfer data stage 100 : control write transfer status stage 101 : control write no data transfer status stage 110 : control transfer sequence error 111 : not assigned can be seen the stage of control transfer. as to the stage shift of control transfer, refer to fig.5 in the later part. (write operation is available when s/w control mode is set) control transfer stage 2-0 vbus input port input data from external vbus is stored. 0: vbus input port is "l" 1: vbus input port is "h" external vbus input data is latched by the positive edge of internal clock. refer to this bit after enabled internal clock operation. 7 dvsq [2:0] 3 6-4 ctsq [2:0] valid vbus w/r usb s/w h/w
usb device controller M66290AGP/fp mitsubishi 17 reset function name bit name bit r - 00h 00h write/read "0" epb_rdy [5:0] endpoint5-0 buffer ready interrupt when buffer becomes ready (read/write enabled) to each endpoint, the bit which corresponds to the number of endpoint changes to "1". the factor of the interrupt is different by the transfer condition of each endpoint. 1. as to ep0 this bit changes to "1" when receive buffer(out) became ready (read enabled) in control write transfer. if it is set to control write continuous receive mode or completed receiving of the data of 255bytes or received short data packet, this bit changes to "1". this bit is not changed even if the transmission buffer(in) became ready (write enabled) in control read transfer. the ready state of the transmission buffer(in) can be known by the buffer empty interrupt. 2. as to ep1 to ep5, when cpu access this bit changes to "1" when each buffer of each endpoint became ready(read/write enabled). this bit also changes to "1" when set the direction of the transfer to in in initialization. 3. as to ep1 to ep5, when dam access if the direction of the transfer is set to out, this bit changes to "1" when received short data packet and then completed dma transfer of received data. in this case, clear is only available to write the bclr command. this bit is not changed if the direction of transfer is set to in. clearance of this flag is different by the transfer direction of endpoint. 1. if the transfer direction is out after set the number of the object endpoint to the "fifo selection register", write bclr command or read all data of the buffer, then flag is cleared. (when dma access, clearance is only available to write bclr command) 2. if the direction is in after set the number of the object endpoint to the "fifo selection register", write ival command or write data into the buffer of maximum packet size (buffer size, if in continuous transmission mode ), then flag is cleared. reserved 5 to 0 15 to 6 w/r usb s/w h/w epb_rdy[5:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 (2-6 ) interrupt status register 1 (address : 1ah)
usb device controller M66290AGP/fp mitsubishi 18 bit bit name name function reset - 00h 00h w/r write/read "0" epb_ nrdy [5:0] endpoint5-0 buffer not ready interrupt to in/out token of each endpoint, if the set of response pid is not nak("00") and if buffer is in not ready state (receive/transmit disabled), the bit which corresponds to the number of endpoint changes to "1". (if the endpoint is control transfer or bulk transfer or interrupt transfer, nak response is executed) if the endpoint is set to isochronous transfer, m66290a does not execute nak response, but when over-run or under-run of endpoint buffer occurred, this bit changes to "1" at the timing of token packet receive end. if it is set to isochronous (out), and if received data has error such as crc, this bit changes to "1" at the timing of transaction end. when "0" is written, status flag is cleared. when "1" is written, flag is not changed. 5 to 0 reserved 15 to 6 w/r usb s/w h/w epb_nrdy[5:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 ( 2-7 ) interrupt status register 2 ( address : 1ch )
usb device controller M66290AGP/fp mitsubishi 19 bit bit name name function reset - 00h 00h w/r write/read "0" epb_ emp_ ovr [5:0] endpoint5-0 buffer empty/size error interrupt when factors below are occurred to each endpoint, the bit which corresponds to the number of endpoint, changes to "1". 1. if the transfer direction is in in each endpoint, when transmission completed of all data which stored in buffer, c by this interrupt, if endpoint is set to double buffer, it can be known that transmission of all data of buffer is completed. and also by this interrupt, it can be known that transmission of ep0 is completed. 2. if the direction is out in each endpoint, when received data which exceeds the maximum packet size in data packet receive, the bit which corresponds to the number of endpoint changes to "1". when "0" is written, status flag is cleared. when "1" is written, status flag is not cleared. 5 to 0 reserved 15 to 6 w/r usb s/w h/w epb_emp_ovr[5:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 ( 2-8 ) interrupt status register 3 ( address : 1eh)
usb device controller M66290AGP/fp mitsubishi 20 (3) control transfer / enumeration in control transfer, there are setup stage, data stage, and status stage. m66290a manages stage and inform cpu the stage shift by interrupt. cpu do stage transact of control transfer according to the interrupt factor. setup stage in setup stage, 8bytes request (setup data) of setup transaction data packet which transferred from host is stored into four registers automatically (request, value, index, and length register). except for device state shift request (set address and set configuration) which can cope with by the automatic response control function, analysis (decode) and execution of contents of request must be done by cpu. by executing the request, it proceeds to data stage or to status stage. data stage data stage executes in transaction or out transaction according to the contents of request. if it is control write transfer, data stage is out transaction and cpu prepares for data receive at the timing of interrupt in setup stage and reads the received data from endpoint fifo when data receive ended. usb bus connect full speed device recognition clock on initializing tr on vbus interrupt usb reset usb reset receive dvst interrupt usb request (control transfer) get xx command ctrt interrupt set response data usb request set address ctrt/dvst interrupt (automatic response available) usb request get xx command ctrt interrupt set configuration ctrt/dvst interrupt (automatic response available) usb request usb request set xx command ctrt interrupt set response data read received data default state address state configured state idle (powered) if it is control read transfer, data stage is in transaction and cpu prepares for data transmit (write into endpoint fifo) at the timing of interrupt in setup stage. m66290a is equipped with control transfer continuous transmit and receive function. after ended data stage, it proceeds to status stage. m66290a device firmware device state figure 3. abstract of enumeration operations status stage status stage executes receive/transmit of null data (data length 0), in both control write and control read transfer. receive/transmit of null data is possible to set control transfer complete enable bit (ccpl) after ended setup stage. control transfer complete enable bit is reset when received setup packet. control transfer executes data transfer using ep0. to both control read and control write, buffer size of ep0 can be set by a unit of 64bytes by "control transfer control register". access to ep0_fifo data register must be done by cpu access. dma transfer can not be set. figure 3. shows the abstract of enumeration operations.
usb device controller M66290AGP/fp mitsubishi 21 setup token out token out token out token out token out token in token in token in token data packet null data packet nak data packet data packet data packet data packet data packet nak ack nak nak ack ack ack ack setup stage data stage status stage int1 int1: ctrt interrupt (setup stage completion) read ep0 request and confirm the contents of request. int2 int2: ctrt interrupt (control write transfer status stage shift) confirm the number of byte of received data and read the received data. by receiving setup token packet, response pid of ep0 is set to nak automatically. by the set of response pid to buf (buffer control), data receive starts. by the set of ccpl, transmit the null data. interrupt, which is occurred by control write transfer status stage shift and by control transfer completion is different by interrupt enable setting. (1) continuous receive mode (control write transfer) setup token in token in token in token in token in token data packet null data packet data packet data packet ack nak nak nak ack ack setup stage data stage status stage int1 int1: ctrt interrupt (setup stage completion) read ep0 request and confirm the contents of request. by receiving setup token packet, response pid of ep0 is set to nak automatically. (2) continuous transmit mode (control read transfer) out token data packet in token ack ack executes transmit data write which is requested, set transmit data length, set response pid to buf (buffer control), and data transmit is started. by the set of ccpl, ack handshake is executed when received null data. interrupt which is occurred by control read transfer status stage shift and by control transfer completion is different by interrupt enable setting. auto-response control function m66290a has auto-response function to device state transition request (set address and set configuration)in control transfer. by the set of "auto-response control register", auto-response mode to set address and to set configuration can be set individually. if the auto-response mode is set, device state transition request can be ended without occurring interrupt. transfer direction of packet : host to m66290a m66290a to host continuous transfer function m66290a has continuous transfer function to transmit/receive continuously of requested data which extend plural of transaction. if continuous transfer mode is set, it can transfer the transmit which data length is set to "ep0 continuous transmit data length register", without occurring interrupt. control read buffer can be set up to 256bytes at a unit of 64bytes. control write buffer can receive continuously up to 255bytes, so secure the area of 256bytes. abstract of control transfer operations figure 4. shows examples of abstraction of control transfer operations. figure 4. examples of abstract of control transfer operations
usb device controller M66290AGP/fp mitsubishi 22 powered state (dvsq="000") suspended state (dvsq="100") suspend detection (dvst) resume detection (resm) default state (dvsq="001") suspended state (dvsq="101") suspend detection (dvst) resume detection (resm) default state (dvsq="010") suspended state (dvsq="110") suspend detection (dvst) resume detection (resm) set address execution (dvst) (deviceaddress=01h to 7fh) *can be set to auto-response usb reset detection (dvst) default state (dvsq="011") suspended state (dvsq="111") suspend detection (dvst) resume detection (resm) set configuration execution (dvst) (configuration value is not equal to 0) *can be set to auto-response set configuration execution (dvst) (configuration value is not equal to 0) *can be set to auto-response usb reset detection (dvst) device state transition m66290a manages device state by h/w. it manages powered, default, address, configured, and suspended state of usb device state. to set_address and set_configuration request in auto-response mode, transfer can be completed without occurring interrupt to cpu. to set_address request, auto-response is executed to set_address request (deviceaddess=01h to 7fh) which device state is in default state, and to figure 5. device state shift other state and to set_address request which deviceaddess is not equal to 01h to 7fh, auto-response is not executed. to set_configuration request, auto-response is executed to set_configuration request (configurationvalue is not equal to 0) which device state is in address state and to set_configuration request (configurationvalue=0) which device state is in configured state. to other state and to set_configuration request which is different of its configurationvalue from the value above, auto-response is not executed.
usb device controller M66290AGP/fp mitsubishi 23 control transfer sequence error control write status stage control write data stage setup stage control read data stage control read status stage control write no data stage status receive short packet or receive in token (control write transfer status stage transition) transmit short packet or receive out token (control read transfer status stage transition) ack transmit (setup stage complete) ack transmit ack transmit (setup stage complete) ack receive (control transfer complete ) ack receive (control transfer complete ) ack receive (control transfer complete ) r eceive error detected figure 6. stage shift of control transfer control transfer stage transition m66290a manages control transfer sequence by h/w. there are setup stage, data stage, and status stage in control transfer stage, as shown in figure 6. and when stage shifts, ctrt interrupt occurs. there are five factors in ctrt interrupt, that is, setup stage end, control write transfer status stage shift, control read transfer status stage shift, control transfer end, and control transfer sequence error. and there are seven errors as follows in control transfer sequence error which can be detected by h/w. if h/w detected control transfer sequence error, response pid is set to stall("1x") automatically. 1. in token packet receive in control write data stage (in token packet receive which did not do ack handshake once to out token packet in data stage) 2. out token packet receive in control write status stage 3. out token packet receive in control read data stage. (out token packet receive which did not do data transfer once to in token packet in data stage). 4. in token packet receive in control read status stage. 5. data packet receive except for null data in control read status stage. 6. out token packet receive in control write no data status stage. 7. data receive which exceeds maximum packet size. in control write data stage, it can not be recognized as sequence error when received data packet which exceeds request wlength value. setup packet (setup stage complete)
usb device controller M66290AGP/fp mitsubishi 24 bit - 00h 00h r - 00h 00h r this fields provides bmrequest of the last setup packet received. this fields provides brequest of the last setup packet received. request register bmrequest type [7:0] brequest [7:0] 7 to 0 requesttype register 15 to 8 bit name name function w/r usb s/w h/w reset - - 0000h r this fields provides wvalue of the last setup packet received. value register wvalue [15:0] 15 to 0 bit bit name name function w/r usb s/w h/w reset - - 0000h r this fields provides windex of the last setup packet received. index register windex [15:0] 15 to 0 bit bit name name function w/r usb s/w h/w reset function name bit name reset - - 0000h r this fields provides wlength of the last setup packet received. length register wlength [15:0] 15 to 0 bit w/r usb s/w h/w wvalue[15:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 brequest[7:0] bmrequesttype[7:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 windex[15:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 wlength d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 ( 3-1 ) request register ( address : 20h ) ( 3-2 ) value register ( address : 22h ) ( 3-3 ) index register ( address : 24h ) ( 3-4 ) length register ( address : 26h )
usb device controller M66290AGP/fp mitsubishi 25 reset bit name - - 00h w/r - - 0 w/r - - 00h w/r 6 7 write/read "0" write/read "0" when "1" is written, control write transfer continuous receive mode is set. control read transfer continuous transmit mode is set when "1" is written in this bit. control write transfer continuous receive mode control read transfer continuous transmit mode appoint the start number of the buffer which is used in control write transfer by a unit of 64bytes. the buffer is available from #00h to #2fh. when control write continuous receive mode is set, it can receive continuously up to 255bytes, so keep the area of buffer of 256bytes (4 blocks). control write buffer start number appoint the start number of the buffer which is used in control read transfer by a unit of 64bytes. the buffer is available from #00h to #2fh. when control read continuous transmit mode is set, it can transmit continuously up to 255bytes, so keep the area of the buffer of 256bytes (4 blocks). control read buffer start number reserved ctrw ctr_rd_ buf_nmb [5:0] 5 to 0 13 to 8 14 ctr_wr_ buf_nmb [5:0] reserved - - 0 w/r ctrr 15 bit name function w/r usb s/w h/w bit name - - 08h w/r write/read "0" set the maximum value of data (byte) which transmit or receive in a packet transfer. set the value of wmaxpacketsize in request. this bit must be set after set the response pid to nak("00"). max packet size ep0_mxps [6:0] 6 to 0 15 to 7 reserved bit name function w/r usb s/w h/w reset ctrr ctrw ctr_rd_buf_nmb[5:0] ctr_wr_buf_nmb[5:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 ep0_mxps[6:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 ( 3-5 ) control transfer control register ( address : 28h ) ( 3-6 ) ep0 packet size register ( address : 2ah )
usb device controller M66290AGP/fp mitsubishi 26 reset name bit write/read "0" - - 0 w/r - - 0 w/r when "1" is written into this bit, automatic response mode of set_address request is set. to the set_address request in automatic response mode, transfer can be completed without occurring the interrupt to cpu. (set of ccpl is not needed) automatic response is done to the set_address request (deviceaddress is equal to 01h to 7fh) which device state is default state. to the other state and to the set_address request which deviceaddress is not equal to 01h to 7fh, automatic response is not done. when "1" is written into this bit, auto-response mode of set_configuration request is set. to the set_configuration request in auto-response mode, transfer can be completed without occurring interrupt to cpu. (set of ccpl is not needed) auto-response is done to the set_configuration request (configurationvalue is not equal to 0) in address device state and to the set_configuration request (configurationvalue is equal to 0) in configured state. to the other state and to the set_configuration request which configurationvale is different from the value above, auto-response is not done. set_address auto-response mode set_configuration auto-response mode astd ascn 0 1 15 to 2 reserved bit name function w/r usb s/w h/w atad ascn d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 (3-7) auto-response control register (address : 2ch) function bit name - - 0 w/r - - 0 w/r - - 0 w/r write/read "0" write/read "0" 0 : control write (out) buffer select 1 : control read (in) buffer select buffer select if this bit is "1", every time when read ep0_fifo register,the value of odln register is counted down. read count mode if this bit is set to "1", data register of fifo turns to 8-bit mode and lower 8 bit[7:0] becomes enable when access the "fifo data register" of endpoint. when transmit data of odd number byte, data must be written in 8-bit mode. when read in 8-bit mode, set to 8-bit mode before data receive. fifo access 8 bit mode isel reserved 9-1 octl 10 reserved rcnt 14 to 11 15 0 bit name w/r usb s/w h/w reset octl rcnt isel d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 (3-8) ep0_fifo selection register (address : 30h)
usb device controller M66290AGP/fp mitsubishi 27 reset function name bit name bit - - 1 r - - 0 w/r - - 0 w/r - - 00 w/r buffer clear if "1" is written into this bit when the selected endpoint is set to in, in buffer effective state flag and the data (byte) which is written are cleared. if ival="1" and bclr="1" is written at the same time, data is cleared but in buffer effective state flag is set.(this is effective to transmit 0 length data) when "1" is written into this bit, if the selected endpoint is set to out, out buffer effective state flag is cleared and read data is also cleared. when "0" is written, this bit is not changed. if this bit is "0", access to ep0_fifo data register is enabled. and when this bit is "0", ival and odln bit shows the effective value. ep0_fifo data register, when read or write, needs cycle time of 200ns (min). (continuous access at 5mhz is available) ep0_fifo ready e0req bclr ival ep0_pid [1:0] if the control read buffer is selected, this becomes in buffer effective state flag. when set to "1", it becomes to transmit data set state (sie read enabled). if data is written which exceeds to the maximum byte of maximum packet size (mxps), this bit is set to "1". when short packet transmit, set this bit to "1" after wrote transmit data. if the ival="1" and bclr="1" is written at the same time, in buffer effective state flag is set. (this is effective to transmit 0 length data) if the control readout) buffer is selected, it becomes out buffer effective state status. status "1" shows that there is data which can be read. this bit shows the effective value when e0req bit is "0". if "1" is written, it is not changed. if "0" is written, flag is not changed. in buffer status setting the response pid. 00 : nak whatever the buffer state is,do nak handshake. 01 : buf response pid is selected by the state of buffer and sequence toggle bit status. (one of ack, nak, and data0/data1) 1x : stall do stall handshake 1. when received setup packet, turns to "00"(=nak) automatically. 2. when received request (set_address, etc.) which is set to automatic response, turns to "01"(=ack) automatically after completed the setup transaction. 3. if sequence error occurred in control transfer,or received data in control write transfer which exceed maximum packet size, this turns to "1x"(=stall) automatically. response pid 11 12 13 15 to 14 w/r usb s/w h/w ccpl ep0_pid[1:0] e0req bclr ival odln[7:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 ( 3-9 ) ep0_fifo control register ( address : 32h )
usb device controller M66290AGP/fp mitsubishi 28 - - xxxx w/r when read, this becomes to receive data fifo register. if it is set to 8-bit mode, lower 8 bit[7:0] is valid. when write, this becomes to transmit data fifo register. if it is set to 8-bit mode, lower 8 bit[7:0] is valid. both for read and write, cycle time of 200ns (min) is needed. (continuous access at 5mhz is available) read when in buffer is selected or write when out buffer is selected is inhibited. ep0_fifo data ep0_fifo [15:0] 15 to 0 bit bit name name function w/r usb s/w h/w reset bit bit name name reset - - 00h w/r write/read "0" set the control read continuous transmit data length (byte). it can be set up to ffh (255bytes). in control read continuous transmit mode, write fifo data (transmit data) after set this register. this is available in control read continuous transmit mode. control read continuous transmit data length sdln [7:0] reserved 14-8 7 to 0 function w/r usb s/w h/w sdln[7:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 ep0_fifo[15:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 ( 3-10 ) ep0_fifo data register ( address : 34h ) (3-11) ep0 continuous transmit data length (address : 36h) name function - - 0 w/r to write "1" into this register, status stage of control transfer can be completed. if this bit is "1" and response pid is buf("01"), null data is transmitted in control write transfer, and do response ack in control read transfer when received null data. if this bit is "0", do response nak in status stage. this flag is reset to "0" when received setup packet. control transfer complete enable ccpl 10 write/read "0" - - 00h r received data length(byte) can be read from this register. if rcnt mode is set, every time when read ep0_fifo data register, it is counted down by -1(8-bit mode) or by -2(16-bit mode). this bit shows effective value when e0req bit is "0". control write receive data length reserved odln [7:0] 9 to 8 7 to 0 bit bit name w/r usb s/w h/w reset
usb device controller M66290AGP/fp mitsubishi 29 construction of endpoint (ep1 to ep5) fifo transfer type epi_typ[1:0] can be set to bulk, interrupt, isochronous transfer. transfer direction epi_dir can be set to in/out double buffer (toggle buffer) epi_dblb can be set continuous transmit/receive epi_rwmd can be set (effective in bulk transfer) buffer size epi_buf_siz[3:0] can be set (up to 1 024bytes by a unit of 64bytes) response pid epi_pid[1:0] can be set to nak, stall, and buf(buffer control). dma transfer epi_dmae can be set receive data read and abandon mode epi_aclr can be set max packet size epi_mxps[9:0] can be set ( 0 to 1023bytes) r egister ep1 to ep5 examples of endpoint fifo setting fifo number memory address endpoint setting 00h to 03h 000h to 0ffh ep0:control write transfer buffer size:256bytes control write continuous receive mode(ctrw) fifo area:256bytes(4 blocks) 04h to 07h 100h to 1ffh ep0:control read transfer buffer size:256bytes control read continuous transmit mode(ctrr) fifo area:256bytes(4 blocks) 08h 200h to 23fh ep2:interrupt transfer(in) buffer size:64bytes fifo area:64bytes(1 block) 09h 240h to 27fh ep4:interrupt transfer(out) buffer size:64bytes fifo area:64bytes(1 block) 0ah to 0bh 280h to 2ffh ep3:bulk transfer(in) buffer size:64bytes double buffer constitution(dblb) fifo area:128bytes(2 blocks) 0ch to 0fh 300h to 3ffh not used:256bytes(4 blocks) 10 h to 2fh 4 00h to bffh ep1:bulk transfer(out) buffer size:1024bytes double buffer constitution(dblb) continuous receive mode(rwmd) fifo area:2kbytes(32 blocks) (4) endpoint and fifo control except for ep0 for control transfer, m66290a can set five endpoints as ep1 to ep5. each of t hese five endpoints (ep1 to ep5) can be set to bulk, interrupt, and isochronous transfer. and yet, another constitution can configurated independently. below are the constitutions to be realized. built-in fifo for endpoint buffer is 3kbytes totally of its memory capacity. this fifo of 3kbytes can divided into each endpoint of ep0 to ep5 and to each endpoint, can assign up to 1024bytes (max) by a unit of 64bytes. buffer size of each endpoint must be set to over the capacity which is set in maximum buffer size. in the buffer size, which is set, bytes of maximum packet size is used for valid. (if set the buffer size to 128bytes to the endpoint which maximum packet size is set to 64bytes, 64bytes are valid) we show se tting examples to each of these buffer of ep0 to ep5 below, and next explain about continuous transmit and receive function, fifo control, dma transfer, and double buffer. continuous transfer function continuous transfer function is to transmit/receive data which extend plural transaction without occurring interrupt to cpu. for ep1 to ep5, this function is effective when transfer type is bulk transfer. in each endpoint, when continuous transfer mode is set, it can transfer data up to the buffer size which is set to the endpoint without occurring interrupt to cpu. to use with double buffer constitution, 1kbytes x2 maximum of buffering is realized. continuous receive mode can receive data packet continuously up to the buffer size which is set, or until receives short packet. if the data to be received is data packet of max packet size, it can receive continuously up to the buffer size without occurring interrupt to cpu, and if the data is data packet (max packet size) which is less than buffer size, interrupt to cpu is not occurred. in bulk transfer, when set max packet size as 64bytes, buffer size as 1024bytes, and fifo constitution as double buffer, when received data of max packet size as 16 times (1024bytes), it became buffer redried enable) and urge to cpu by interrupt to read received data. when received short packet, ends the continuous receive and buffer became redried enable). continuous transmit mode can transmit data packet continuously up to buffer size which is set. short packet transmit can be done to set ival flag. and it is needed to set ival flag to transmit a multiple data of maximum packet size which is less than buffer size. by set null data transmit addition mode, when write a multiple data of max packet size into buffer and transmit, null data can be transmitted automatically after the last packet is transmitted .
usb device controller M66290AGP/fp mitsubishi 30 fifo control access to endpoint buffer of ep0 to ep5 is done by three fifo data registers. one is only for ep0 and others are common to ep1 to ep5. common data registers are divided into two, because accessing is different, that is for cpu access and for dma transfer. which endpoint of ep1 to ep5 to be accessed can be selected to set each fifo selection register. endpoint ep0 ep1 to ep5 accessing cpu access cpu access dma transfer register name ep0_fifo data register cpu _fifo data register dma _fifo data register each of three fifo registers has functions as follows. and these functions can be used to set "each fifo selection/control register". short packet transmission function (ival : in buffer status bit) transmit/receive buffer clear function (bclr : buffer clear bit) null data (data length 0) transmit function (ival & bclr) data length (8/16 bit) set function (octl : register 8bit mode bit) received data length count down function (rcnt : read count mode bit) *: there is none for dma transfer access to cpu_fifo data register when interrupt occurred, to know the endpoint which requested access, access the "interrupt status register 0/1" and by checking the interrupt status flag and know the endpoint which requested access, and then set endpoint to be accessed by "cpu_fifo selection register". if there is no change of endpoint setting, it is not needed to set again the cpu access endpoint appointment bit. data transfer procedure data which is set to endpoint fifo, is sent to usb bus by lsb first. when store the received data from usb bus to endpoint fifo, it is as the same as above. d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 1 16 time scale (data send procedure to usb bus) dma transfer to endpoint of ep1 to ep5, 16bits width or 8bit width of dma transfer is available. each endpoint of ep1 to ep5 can be set to cpu access mode or dma access mode by set of "epx configuration register 1" mentioned later. dma transfer is realized to hand shake with external dmac and d req , dack signal. dreq is asserted when endpoint buffer, which is set to dma transfer mode, became ready. the means of buffer ready state is, if the endpoint transfer direction is set to out (recive data from host) buffer ready means that in read enable state, if the endpoint transfer direction is set to in(transmit data to host) buffer ready means that in write enable state. setting the transfer direction can be done by "epi configuration register 0" to each endpoint. when dack comes from external dmac after asserted dreq, dreq is negated. in dma transfer, dack is dealt equivalently with cs signal and dm a_fifo address appointment. appoint read or write operation by rd or wr signal. this dma transfer can be used only for single transfer, which transfers one word (16bit or 8bit) by one time dreq start. in dma transfer, as same as the cpu access, occurs endpoint buffer not ready interrupt and endpoint buffer empty interrupt according to endpoint buffer state. but as to endpoint buffer ready interrupt, it is not same as the cpu access as follows. in dma transfer, endpoint buffer ready interrupt is not occurred if the transfer direction is in. if the transfer direction is out, interrupt is occurred when received short data packet and ended data transfer of all data which received in dma transfer. occurring of endpoint buffer ready interrupt and to refer dma_dtln, it can be known that short data packet was received. dma_dtln shows the number of byte of short data packet, or in the continuous receive mode it shows the number of byte of received data before short data packet receive.
usb device controller M66290AGP/fp mitsubishi 31 after "data1" read end "data2" receive end "data3" receive start "data1" read start "data2" receive start "data1" receive end "data1" receive start before "data1" read end "data2" receive end "data1" read end when data receive ended, the buffer is set to ready state (read enable) and occurs intr interrupt continuous receiving is available before data read. in out token receive to this intn interrupt and do nak handshake . endpoint, m66290a occurs it becomes receive enable after read of data1 ended. and occurs intr interrupt because the buffer is ready. m66290a occurs intr interrupt because the buffer is ready. data1 data1 data2 data2 receiving data buffer1 buffer2 usb side cpu bus side buffer2 buffer1 data receive available data receive completed data read available buffer2 buffer1 data1 data2 receiving data data read available data1 buffer2 buffer1 in in in receiving data reading data buffer2 buffer1 data receive completed data receive impossible reading data out data1 out buffer1 buffer2 data receive enable data read available data2 buffer1 buffer2 data receive available data read available data2 buffer1 buffer2 data2 data3 receiving data data read available in data : data exists in buffer (1) receiving below are the receive status examples of the endpoint which is set to double buffer. endpoint buffer status figure 7. double buffer activities-1 double buffer operations the endpoint fifo of ep1 to ep5 can be set to double buffer constitution. so a double of transfer data of its buffer size, which is set, can be stored.
usb device controller M66290AGP/fp mitsubishi 32 after "data1" transmit end "data2" write end "data3" write start "data1" write end "data1" write start in token receive before "data1" transmit end "data2" write end "data1" transmit end data1 data1 data1 data transmit impossible buffer1 buffer2 usb side cpu bus side buffer1 buffer2 writing data buffer2 buffer1 data1 data transmit available data write available data2 buffer2 buffer1 out transmitting data writing data buffer2 buffer1 transmitting data data write completed in data2 buffer1 buffer2 data transmit avalable data write avalable buffer1 buffer2 data transmit avalable buffer1 buffer2 data3 data2 writing data data : data exists in buffer (2) transmitting below are the transmit status examples of the endpoint which is set to double buffer. endpoint buffer status figure 8. double buffer activities-2 "data1" transmit start "data2" write start data write available data transmit impossible out in data writeimpossible data2 data2 data write avalable can not transmit because the transmit buffer is in notready. request cpu to prepare transmit data by intn interrupt data write is available during data transmitting. when data transmit ended, it occurs intr interrupt because the buffer is in ready. end of data write of maximum packet size or to set(short packet transmit) set status, and transmit becomes enable. and occurs intr interrupt because the buffer is in ready (write enable). ival flag, it becomes transmit data end of data write of maximum packet size or to set (short packet transmit) set status, and transmit becomes enable. ival flag, it becomes transmit data when data transmit ended, because the buffer is in it occurs intr interrupt ready. in data transmit avalable in
usb device controller M66290AGP/fp mitsubishi 33 reset name bit - - 0000 w/r - - 0 w/r write/read "0" appoint the cpu access endpoint. "0001"=ep1,"0010"=ep2,"0011"=ep3, "0100"=ep4,"0101"=ep5 ep0 can not be appointed. don't change the setting in writing (in) or in reading (out). change of the setting of the endpoint of direction in must be done after confirmed that ival="0" and creq="0", or ival="1" and creq="1". change of the setting of the endpoint of direction out must be done after confirmed that ival="1" and creq="0", or ival="0" and creq="1". cpu access endpoint 15 rcnt if this bit is "1", every time when read cpu_fifo register, cpu_dtln register value is counted down. read count mode cpu_ep [3:0] reserved 14 to 4 3 to 0 bit name function w/r usb s/w h/w cpu_ep[3:0] rcnt d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 (4-1) cpu_fifo selection register (address : 40h) function bit name - - 0 w/r write/read "0" if the selected endpoint is set to in, this becomes in buffer effective state flag. when set to "1", it becomes transmit data set state. (sie is available to read) when the data (byte) which exceeds to the maximum packet size (mxps) is written, this bit is set to "1". in short packet transmit, set this bit to "1" after wrote the transmit data. if ival="1" and bclr="1" is written at the same time, the effective state flag is set. (this is effective to transmit 0 length data) if the selected endpoint is set to out, it becomes to out buffer effective state status. status "1" shows that there is data which is available to read. when creq bit is "0", this bit shows effective value. this bit is not changed when "1" is written. flag is not changed when "0" is written. in buffer status ival 13 reserved 15, 14 bit name w/r usb s/w h/w reset cpu_dtln[10:0] creq bclr ival d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 (4-2) cpu_fifo control register (address : 42h)
usb device controller M66290AGP/fp mitsubishi 34 bit bit name name function - - 000h r - - 1 r - - 0 w/r cpu_fifo ready if this bit is "0", access to cpu_fifo data register is available. and if this bit is "0", the bit of ival and cpu_dtln bit shows the effective value. when read or write to cpu_fifo register, 200ns (min) of cycle time is needed. (continuous access at 5mhz is available) if the access end point is changed, 200ns (min) of recovery time is needed. when read this register, receive data length (byte) appears. when rcnt mode is set, every time when read cpu_fifo register, it is counted down by -1 (8-bit mode) or by -2 (16-bit mode). if rcnt mode is not set, this register turns to 000h after all of received data is read. this bit shows effective value when creq bit is "0". cpu_fifo receive data length if the selected endpoint is set to in, when "1" is written into this bit, the in buffer effective state flag and the data (byte) which is written are cleared. if ival="1" and bclr="1" is written at the same time, data is cleared but the in buffer effective state flag is set. (this is effective to transmit 0 length data) if the selected endpoint is set to out, when "1" is written into this bit, the out buffer effective state flag and the read data (byte) are cleared. if it is set to double buffer, the state of write/read enable buffer for cpu is cleared. to set the epi_aclr, usb bus buffer is cleared. this bit is not changed when "0" is written. buffer clear cpu_dtl n[10:0] 10 to 0 11 12 creq bclr w/r usb s/w h/w reset
usb device controller M66290AGP/fp mitsubishi 35 - - xxxx w/r if the selected endpoint is set to out, this becomes to receive data fifo register. if the selected endpoint is set to in, this becomes to transmit data fifo register. if the selected endpoint is set to 8-bit mode, lower 8 bit [7:0] is valid. when read or write, 200ns (min) of cycle time is needed. (continuous access at 5mhz is available) read operation when direction in is appointed or write operation when direction out is appointed, write operation is inhibited. cpu_fifo data cpu_fifo [15:0] 15 to 0 bit bit name name function w/r usb s/w h/w reset - - 0 w/r set the operation mode of dma transfer. 0 : high speed transfer mode 1 : one word transfer mode in high speed transfer mode, when endpoint buffer is in read/write enable in the state that dma transfer enable, dreq is asserted. in one word transfer mode, when endpoint buffer is in read/write enable in the state that dma transfer enable and dack="h", dreq is asserted. in both mode, dreq detects dack="l" and is negated. dma operation mode mode 15 reset function name bit name bit write/read "0" reserved 14 to 9 - - 0 w/r - - 0000 w/r write/read "0" appoint the endpoint for dma transfer. "0001"=ep1,"0010"=ep2,"0011"=ep3, "0100"=ep4,"0101"=ep5 ep0 can not be appointed. don't change the setting during write (in) or read (out). change of the setting of the endpoint of direction in must be done after confirmed that ival="0" and dreq="0", or ival="1" and dreq="1". change of the setting of the endpoint of direction out must be done after confirmed that ival="0" and dreq="1". dma transfer endpoint if this bit is "1", endpoint buffer which is appointed by dma_ep[3:0] is enable to write or when read is enable, dreq is asserted. if "0" is written in dma transferring, dma transfer is forced to end. dma transfer enable reserved dma_ep [3:0] 3 to 0 7 to 4 dmaen 8 w/r usb s/w h/w mode dmaen dma_ep[3:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 (4-3) cpu_fifo data register (address : 44h) ( 4-4 ) dma_fifo selection register (address : 48h ) cpu_fifo[15:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14
usb device controller M66290AGP/fp mitsubishi 36 function name bit name bit reset - - 0 w/r - - 0 w/r write/read "0" if "1" is written into this bit when the selected endpoint is set to in, in buffer effective state flag and the data (byte) which is written are cleared. if the ival="1" and bclr="1" is written at the same time, the data is cleared but the in buffer effective state flag is set.(this is effective to transmit 0 length data) if "1" is written into this bit when the selected endpoint is set to out, out buffer effective state flag and the read data (byte) are cleared. if it is set to double buffer, the state of buffer which can be read or write for cpu bus is cleared. to set the epi_aclr, usb bus buffer is cleared. this bit is not changed when "0" is written. buffer clear if the selected endpoint is set to in, this becomes in buffer effective state flag. when set to "1", it becomes transmit data set state. (sie is available to read) when the data (byte) which exceeds to the maximum packet size (mxps) is written, this bit is set to "1". in short packet transmit, set this bit to "1" after wrote the transmit data. if ival="1" and bclr="1" is written at the same time, the in buffer effective state flag is set to "1". (this is effective to transmit 0 length data) if the selected endpoint is set to out, it becomes to out buffer effective state status. status "1" shows that there is data which is available to read. when creq bit is "0", the value of this bit is effective. this bit is not changed when "1" is written. flag is not changed when "0" is written. in buffer status 12 bclr ival 13 reserved 15, 14 w/r usb s/w h/w dma_dtln[10:0] dreq bclr ival d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 (4-5) dma_fifo control register (address : 4ah)
usb device controller M66290AGP/fp mitsubishi 37 name bit name - - xxxx w/r if the selected endpoint is set to out, this becomes to receive data fifo register. if the selected endpoint is set to in, this becomes to transmit data fifo register. if the selected endpoint is set to 8-bit mode, lower 8 bit [7:0] are valid. read operation when the endpoint appointed direction in, or write operation when the endpoint appointed direction out, is inhibited. dma_fifo data dma_fi fo[15:0] 15 to 0 bit function w/r usb s/w h/w reset dma_fifo[15:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 ( 4-6) dma_fifo data register (address : 4ch) reset bit - - 1 r - - 000h r if this bit is "0", then access is available to dma_fifo register. and if this bit is "0", then the bit of ival and dma_dtln is valid. this bit is used as dma request signal (dreq). dma_fifo ready dreq when read this register, receive data length (byte) is appears. this bit is valid when dreq bit is "0". dma_fifo receive data length dma_dt ln[10:0] 10 to 0 11 bit name name function w/r usb s/w h/w
usb device controller M66290AGP/fp mitsubishi 38 appoint the first number of the buffer of a unit of 64bytes. buffer exists from #00h to #2fh. buffer size(double of the buffer size in double buffer mode), which is appointed from the first, is secured for endpoint buffer. set that plural of endpoint do not occupy the same buffer area. if "1" is written into this bit, continuous transfer mode of endpoint is set. when the direction of endpoint is set to out, then it is set to continuous receive mode. and when the direction of endpoint is set to in, then it is set to continuous transmit mode. continuous receive mode can receive data packet up to the buffer size which is set, or can receive continuously before receives short packet. continuous transmit mode can transmit data packet up to the buffer size which is set, and transmission of short packet can be done by set the ival flag. in data packet (max packet size) receive which is less than buffer size, interrupt to cpu does not occur. continuous transfer mode is effective only in bulk transfer. function name bit name bit reset - - 0 w/r continuous transfer mode (only for bulk transfer) - - 0 w/r set the constitution of endpoint buffer. 0 : single buffer mode 1 : double buffer mode in double buffer mode, double of the buffer size is taken as the endpoint buffer. double buffer mode epi_dblb 7 - - 00 w/r - - 0 w/r - - 0 w/r - - 0000 w/r - - 00h w/r 6 epi_ rwmd set endpoint buffer size at a unit of 64bytes. "0000"=64bytes, "0001"=128bytes, ...., "1110"=960bytes, "1111"=1024bytes to set the sequence toggle bit mode of interrupt transfer. 0 : alternation data toggle bit mode (only toggled when transfer completed with no problem) 1 : continuous toggle bit mode (whatever the hand shake exists or the types are, it toggles every time when data packet is transmitted ) this is effective when endpoint is set to interrupt(in) transfer. to set the transfer direction of endpoint 0 : out ( receive data from host ) 1 : in ( transmit data to host ) when changed the state of transfer direction, clear (epi_aclr) the endpoint buffer. to set the transfer type of endpoint. 00 : not configured 01 : bulk transfer 10 : interrupt transfer 11 : isochronous transfer buffer start number epi_buf_ nmb[5:0] buffer size epi_buf_ siz[3:0] interrupt toggle mode epi_itmd transfer direction epi_dir transfer type epi_typ [1:0] 11 to 8 12 5 to 0 13 15 to 14 w/r usb s/w h/w rwmd dblb epi_typ[1:0] dir itmd epi_buf_siz[3:0] epi_buf_nmb[5:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 (4-7) epi configuration register 0 ( i=1 to 5) (address : ep1=60h, ep2=64h, ep3=68h, ep4=6ch, ep5=70h) the epi configuration register 0 must be set in a state of response pid is nak("00").
usb device controller M66290AGP/fp mitsubishi 39 set the maximum data size (byte) to transmit/receive in one packet transfer. set the value of wmaxpacketsize in request. when this bit is set to "1", fifo data register becomes 8-bit mode and when accessed "fifo data register" of endpoint, lower 8bit[7:0] becomes effective. when transmit odd number of byte, it is needed to write in 8-bit mode. when read in 8-bit mode, set to 8-bit mode before data receive. when the selected endpoint is set to out and if this bit is set to "1", out buffer effective flag and read data (number of byte) is cleared. in this state(out buffer does not become effective state), sie side writes data from host into out buffer but cpu side does not read. when se t this bit to "1", whatever the transfer direction is, endpoint buffer (all buffer of single/ double buffer) are cleared. when clear the endpoint buffer, set this bit to "1" and then set again to "0". to set this bit as "1", null data addition transmit mode is set . in the endpoint which is set to continuous transmit mode, when write a multiple data of maximum packet size into buffer and transmit, null data is transmitted automatically after transmitted the last packet. this setting is effective when continuous transmit mode is set. set response pid. 00 : nak whatever the buffer state is, do nak handshake. 01 : buf response pid is selected according to the state of buffer and sequence toggle bit. (in bulk/interrupt transfer, one of ack, nak, data0, and data1) 1x : stall do stall handshake. if the transfer direction of selected endpoint is out, when received data which exceeded maximum packet size (mxps), it becomes "1x" (=stall) automatically. bit bit name name function reset - - 0 w/r null data addition transmit mode - - 040h w/r - - 0 w/r - - 0 w/r - - 0 w/r - - 00 w/r 10 epi_ nulmd epi_ aclr set the access mode to endpoint buffer. 0 : cpu access mode 1 : dma transfer mode max packet size epi_ mxps [9:0] fifo access 8 bit mode epi_octl out buffer automatic clear mode dma transfer mode epi_ dmamd response pid epi_ pid [1:0] 11 12 9 to 0 13 15, 14 w/r usb s/w h/w nulmd dmamd epi_mxps[9:0] octl aclr epi_pid[1:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d15 d13 d14 (4-8) epi configuration register 1 ( i=1 to 5 ) (address : ep1=62h, ep2=66h, ep3=6ah, ep4=6eh, ep5=72h) the epi configuration register 1 must be set in a state of response pid is nak("00").
usb device controller M66290AGP/fp mitsubishi 40 -55 to +150 400 20 -0.3 to v cc +0.3 -0.3 to v cc +0.3 -0.3 to +4.2 c mw ma v v v unit ratings parameter storage temperature power dissipation output current output voltage input voltage supply voltage t stg p d i o v o v i v cc symbol v 5.25 0 input voltage ( only for vbus input ) v i(vbus) operating temperature output voltage input voltage supply voltage supply voltage parameter input rise, fall time t r , t f symbol limits schmidt trigger input normal input 5 500 ms +70 +25 0 v cc 0 v cc 0 0 max. typ. min. 3.6 3.3 3.0 ns c v v v v unit t opr v o v i gnd v cc absolute maximum ratings recommended operating conditions
usb device controller M66290AGP/fp mitsubishi 41 notes 1 : all input and bidirection pins except for xin ( except for usb buffer ) 2 : int,dreq,tdo output pins 3 : d15-0 input /output pins 4 : vbus input pins 5 : test1,test2,tck input pins 6 : trst,tms,tdi input pins note 3 note 2 xout note 1 xin oscillator disable,pll disable, usb transceiver enable, tron=h/l output vi=vcc or gnd fixed,vcc = 3.6v oscillator disable,pll disable, usb transceiver disable, tron=h/l output vi=vcc or gnd fixed,vcc = 3.6v suspend state f(xin)=4 8mhz , v cc = 3.6v usb transmit state oscillator disable,pll disable, usb transceiver disable, tron=h/l output vi=vcc or gnd fixed,vcc = 3.6v h/w reset state supply current in static mode i cc(s) 2 4 100 55 ma ua 200 30 d15-0 ,tdo v 0.4 i ol = 2ma "l" output voltage v ol v 2.6 i oh = -2ma v cc = 3.0v "h" output voltage v oh k w 50 note 5 pull down resistance r dt k w 100 note 4 pull down resistance r dv 10 40 note 6 50 k w pull up resistance r u v 0.4 i ol = 50ua "l" output voltage v ol v 2.6 i oh = -50ua v cc = 3.0v "h" output voltage v oh v cc = 3.6v v cc = 3.6v v cc = 3.0v v cc = 3.3v v cc = 3.0v v cc = 3.6v unit limits symbol parameter condition 0 0.9 2.6 -10 -10 10 10 ma ua ua ua ua v o = gnd v o = v cc v i = gnd i ol = 4ma v i = v cc i oh = -4ma "h" input current "l" input current "h" output current in off status "l" output current in off status average supply current in operation mode i cc(a) i ozl i ozh i il i ih v 0.4 "l" output voltage v ol v ih 1.65 0.5 2.4 1.4 max. typ. min. 3.6 2.52 ua v v v v v "h" output voltage threshold voltage in negative direction threshold voltage in positive direction "l" input voltage "h" input voltage v oh v t- v t+ v il electrical characteristics
usb device controller M66290AGP/fp mitsubishi 42 unit output resistance v cc = 3.3v v cc = 3.6v v cc = 3.0v | (d+)-(d-) | limits symbol parameter test condition 15 15 4 4 v 2.8 3.6 10 -10 7 7 rl of 15k w to gnd rl of 1.5k w to 3.6v "h" output voltage "l" output voltage v o h 0.8 2.5 -10 w w v o =3.3v v o =3.6v v o =0v v o =0v output resistance r o(nch) r o(pch) m a 10 "h" output current in off status i ozh v di 0.3 2.0 0.8 max. typ. min. 0.2 m a v v v v "l" output current in off status single ended receiver threshold differential common mode range differential input sensitivity i ozl v ol v se v cm (1) dc characteristics unit c l=50pf t r/ t f % 110 90 symbol parameter test condition limits 10% to 90% of the data signal 10% to 90% of the data signal rise/fall time matching trfm c l=50pf c l=50pf 20 1.3 4 20 v 2.0 output signal crossover voltage v crs t r max. typ. min. 4 ns ns fall transition time rise transition time t f ( 2 ) ac characteristics electrical characteristics (usb)
usb device controller M66290AGP/fp mitsubishi 43 cl=50pf ns 60 dreq output enable time after control td(ctrl- dreq) ns 2 0 dreq output enable time after dack td(dackh- dreq) 30 30 ns tdo output enable time after tck td(tck- tdov) ns 60 dreq "h" pulse width twh(dreq) ns 0 data valid time after control tv(ctrl) ns tdo output disable time after tck td(tck- tdox) int "h" pulse width 320 twh(int) ns 60 int disable propagation time td(wr-int) ns ns 60 dreq disable propagation time td(dack- 0 0 symbol parameter test condition limits unit ns ns 20 data output disable time after control tdis(ctrl) 20 data output enable time after control ten(ctrl) ta(a) 30 max. typ. min. 30 ns ns control access time address access time ta(ctrl) 83 ns 100 trst "l" pulse width tw(trst) 30 ns trst "l" pulse width td(ctrl- dack) ns 20 tdi,tms setup time th(tdi-tck) ns 20 tdi,tms setup time tsu(tdi-tck) ns 40 tck "l" pulse width tw(tckl) ns 40 tck "h" pulse width tw(tckh) ns 100 tck cycle time tc(tck) ns 100 control start time after reset tst(rst) ns 100 reset pulse width tw(rst) ns 200 fifo access cycle time tw(cycle) ns control recovery time trec(ctrl) unit limits test condition parameter symbol 0 0 tsu(a) 20 30 max. typ. min. 30 ns ns ns ns ns data hold time data setup time control pulse width address hold time address setup time th(d) tsu(d) tw(ctrl) th(a) switching characteristics timing requirements
usb device controller M66290AGP/fp mitsubishi 44 measurement circuit item tdis(ctrl(lz)) tdis(ctrl(hz)) ta(ctrl(zl)) ta(ctrl(zh)) sw1 close open close open sw2 open close open close 1. terminals except for usb buffer block p.g dut 50ohm input vcc cl cl rl=1kohm sw1 sw2 rl=1kohm d15-0, tdo other output vcc (1) input pulse level : 0 to 3.3v input pulse rise/fall time : tr=tf=3ns input timing voltage : 1.65v output timing voltage : vcc/2 (tdis(lz) is measured at 10% of output, tdis(hz) is measured at 90% of output) (2) capacitance cl includes stray capacitance and probe capacitance. 2 . usb buffer block dut vcc cl rl=1.5kohm vcc rl=27ohm rl=27ohm cl d+ d- gnd rl=15kohm rl=15kohm (1) tr, tf is measured from 10% to 90% of output. (2) capacitance cl includes stray capacitance and probe capacitance.
usb device controller M66290AGP/fp mitsubishi 45 d15 to 0 a6 to 1 tsu(d) tw(ctrl) th(d) data input is established th(a) tsu(a) d15 to 0 a6 to 1 ten(ctrl) tw(ctrl) tdis(ctrl) th(a) ta(a) tv(ctrl) ta(ctrl) cs ,rd cs ,wr tw(cycle) tw(cycle) (1) write timing (2) read timing trec(ctrl) trec(ctrl) timing diagram address is established data output is established address is established (note 1) (note 2) (note 3) note 1 : tw(cycle) is needed when access fifo. note 2 : write is done in the overlap period when cs and wr is active "l". spec from the positive edge is valid from the fastest inactive signal. spec of pulse width is valid of the overlap period of active "l". note 3 : read is done in the overlap period of cs and rd is active "l" spec from the negative edge is valid from the latest signal. spec from the positive edge is valid form the fastest inactive signal. spec of pulse width is valid during active "l" overlap period.
usb device controller M66290AGP/fp mitsubishi 46 d15 to 0 dreq tsu(d) tw(ctrl) th(d) twh(dreq) td(dack-dreq) d15 to 0 ten(ctrl) tw(ctrl) tdis(ctrl) tv(ctrl) ta(ctrl) rd wr (3) dma transfer timing -1 (3-2) read timing -1 dack dreq twh(dreq) td(dack-dreq) dack trec(ctrl) trec(ctrl) td(ctrl-dreq) td(ctrl-dreq) data output is established data input is established (note 4) (note 6) (note 4) (note 5) note 4 : inactive condition of dreq is dack="l" and when next dma transfer exists, spec when dreq turns to active is valid the latest one of twh(dreq) or td(ctrl-dreq). note 5 : write is done in the overlap period when dack and wr is active "l". spec from the positive edge is valid from the fastest inactive signal. spec of pulse width is valid of the overlap period of active "l". note 6 : read is done in the overlap period of dack and rd is active "l" spec from the negative edge is valid from the latest signal. spec from the positive edge is valid form the fastest inactive signal. spec of pulse width is valid during active "l" overlap period. in case of full speed transfer mode (dma operation mode register : mode=0) (3-1) write timing -1
usb device controller M66290AGP/fp mitsubishi 47 d15 to 0 dreq tsu(d) tw(ctrl) th(d) td(dack-dreq) wr (3-4) read timing -2 dack td(ctrl-dreq) (note 4) (note 5) note 4 : inactive condition of dreq is dack="l" and when next dma transfer exists, spec when dreq turns to active is valid the latest one of twh(dreq) or td(ctrl-dreq). note 5 : write is done in the overlap period when dack and wr is active "l". spec from the positive edge is valid from the fastest inactive signal. spec of pulse width is valid of the overlap period of active "l". note 6 : read is done in the overlap period of dack and rd is active "l" spec from the negative edge is valid from the latest signal. spec from the positive edge is valid form the fastest inactive signal. spec of pulse width is valid during active "l" overlap period. (3-3) write timing -2 rd tw(ctrl) td(ctrl-dreq) tsu(d) th(d) d15 to 0 dreq ta(ctrl) tw(ctrl) tv(ctrl) td(dack-dreq) wr dack td(ctrl-dreq) (note 4) (note 6) rd td(ctrl-dreq) tw(ctrl) ta(ctrl) tv(ctrl)
usb device controller M66290AGP/fp mitsubishi 48 d15 to 0 dreq tsu(d) tw(ctrl) th(d) twh(dreq) td(dack-dreq) d15 to 0 ten(ctrl) tw(ctrl) tdis(ctrl) tv(ctrl) ta(ctrl) rd wr (4) dma transfer timing -2 (4-2) read timing -1 dack dreq twh(dreq) td(dack-dreq) dack trec(ctrl) trec(ctrl) td(dackh-dreq) data output is established data input is established (note 7) (note 6) (note 7) (note 5) note 7 : inactive condition of dreq is dack="l" and when next dma transfer exists, spec when dreq turns to active is valid the latest one of twh(dreq) or td(dackh-dreq). note 5 : write is done in the overlap period when dack and wr is active "l". spec from the positive edge is valid from the fastest inactive signal. spec of pulse width is valid of the overlap period of active "l". note 6 : read is done in the overlap period of dack and rd is active "l" spec from the negative edge is valid from the latest signal. spec from the positive edge is valid form the fastest inactive signal. spec of pulse width is valid during active "l" overlap period. in case of one word transfer mode (dma operation mode register : mode=1) (4-1) write timing -1 td(dackh-dreq) td(ctrl-dack) td(ctrl-dack)
usb device controller M66290AGP/fp mitsubishi 49 td(ctrl-int) cs ,wr (5) interrupt timing int twh(int) tst(rst) cs ,wr (6) reset timing rst,trst tw(rst) (note 8) note 8 : write is done in the overlap period when cs and wr is active "l". spec from the positive edge is valid from the fastest inactive signal.
usb device controller M66290AGP/fp mitsubishi 50 th(tck-tdi) tdi,tms (7) jtag timing tck tw(tckh) tw(trst) trst tdo tw(tckl) tc(tck) tsu(tdi-tck) td(tck-tdox) td(tck-tdov)
usb device controller M66290AGP/fp mitsubishi 51 11 9 8 boundary scan register (jtagbsr) bypass register (jtagbpr) id code register (jtagidr) decoder command register (3bits) (jtagir) tap controller data register group tdi tms tck trst 10 12 tdo m66290a abstraction of jtag m66290a has jtag (joint test action group) interface which meets ieee 1149.1 test access port spec. this jtag interface can be used for input/output path (boundary scan path) for boundary scan test. further information as to jtag test access port, refer to "ieee std. 1149.1a-1993". pin descriptions pin description which relates to jtag interface of m66290a are as follows. test clock input (tck) clock input into test circuit. test data input (tdi) synchronous serial input to input test command code and test data. data is sampled by the positive edge of tck. test data output (tdo) synchronous serial output to output test command code and test data. output data changes by the negative edge of tck and is output only in the state of shift-ir or shift-dr. in other state,keeps "z". test mode input (tms) t est mode select input to control status shift of test circuit. this is sampled by the positive edge of tck. test reset input (trst) "l" active test reset input to initialize the test circuit asynchronously. to assure this reset function, keep tms input as "h" when this signal changes from "l" to "h". jtag circuit constitution jtag circuit of m66290a is constituted by the blocks as follows. (1) command register which keeps command code which is fetched through the boundary scan path. (2) data register group which is accessed through the boundary scan pass. (3) test access port (tap) controller to control the status shift of jtag block. (4) control logic for input select, output select, and so.
usb device controller M66290AGP/fp mitsubishi 52 pause-ir update-ir 1 1 0 0 1 0 1 1 0 1 1 0 1 0 0 0 0 a y b a/b d q t d q t shift-dr/ir clock-dr/ir update-dr/ir 0 0 1 0 1 1 1 1 0 1 0 0 0 exit2-ir exit1-ir shift-ir capture-ir select-ir-scan exit2-ir select-dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr test-logic-reset run-test-/idle 1 data input from previous cell input select test reset parallel output stage data output to next cell shift register stage note: 0,1 shows the status of tms input signal figure. status shift of tap controller abstract of jtag operations there are four basic access to command register and to data register. and the access is executed based on the status shift of tap controller. tap controller is shifted of its status by the tms input and make a control signal which is needed to each state. capture operation result of the boundary scan test or the fixed data which is defined to each register, is sampled. for operation, load the input data into shift register stage. shift operation through the boundary scan path, access from external is done. m66290a set the data from external and at the same time, output the data which is sampled by capture operation. for register operation, right shift is executed among shift register stage of each bit. figure. basic construction of jtag related register ir path sequence update operation in shift operation, drive the data which is set by external. for register operation, transfer the value which is set to shift register stage, to parallel output stage. jtag interface shifts the internal state according to tms input, and do two kinds of operations as follows. both are basically executed in turn of "capture -> shift -> update". set the command code into command register and when path sequence comes, select the data register which is the object of the operation. d r path sequence to selected data register, refer or set the data.
usb device controller M66290AGP/fp mitsubishi 53 jtag registers command registers command register is constituted by 3 bits register which keeps command code, and is set in the ir path sequence. data register, which is selected in the following path sequence, is determined by the command which is set into the command register. initial value in test reset is idcode command. until the command code is set from external, idcode register is kept selecting as the data register. m66290a supports three commands (extest, sample/preload, and bypass) which are established as essential by ieee 1149.1 and the device recognize register access command (idcode). below are the commands and the related code. extest (command code : b'000) executes outside circuit connection test and on board connection test. reads the tdi input into the "boundary scan register" and outputs the contents of "boundary scan register" from tdo. idcode (command code : b'001) selects the "idcode register" and outputs the device and company discrimination data from tdo. sample/preload (command code : b'010) samples the circuit status in operation and outputs it from tdo, and at the same time, inputs the data from tdi which will be use in the next boundary scan test and set into the "boundary scan register" previously. bypass (command code : b'111) selects the "bypass register" and executes the refer and the set of the data. don't set the command code except for above. data registers (1) boundary scan register (jtagbsr) this is for boundary scan test and is assigned to each terminal of m66290a which is related to jtag. boundary scan register is connected between tdi and tdo terminal, and is selected when "extest command" is ordered. this register captures the status of input terminal or the output value from internal logic circuit in the state of capture-dr. in the state of shift-dr, input the data for boundary scan test parallely outputting the sampled value. and set terminal function (in/out of bidirectional terminal or direction of 3-state output) and output value. as to the jtag related terminal and the structure of boundary scan, refer to bsdl specially. (2) bypass register (jtagbpr) bypass register is one bit register to bypass the boundary scan path when m66290a is not the object in boundary scan test. bypass register is connected between tdi and tdo terminal, and is selected when "btpass command" is ordered. in the state of capture-dr, "0" is loaded. (4) idcode register (jtagidr) idcode register is a register of 32bits to discriminate the device and the company, and keeps information as follows. idcode register is connected between tdi and tdo terminal, and is selected when "idcode command" is ordered. idcode data is loaded in capture-dr state and is output from tdo in shift-dr state. 1. version information (4bits) 2 . part number (16bits) : b'0000 : b'0001 1000 1001 0010 (binary code of "6290") 3 . company id (11bits) : b'000 0001 1100 (jedec code of mitsubishi) 4 . lsb (1bit) : b'1 (fixed)
|
